1. Field of the Invention
The present invention relates to a semiconductor memory device and control method thereof and, more particularly, to a memory card based on an address translation table scheme of associating, in a one-to-one correspondence, a logical block address used when a host apparatus externally accesses a memory with a physical block address (actual block address) in the memory.
2. Description of the Related Art
A memory card which uses a nonvolatile semiconductor memory such as a flash memory serves as a medium for recording music and video data (e.g., see U.S. Pat. No. 6,845,438). One example of such flash memory used in a memory card is a NAND flash™ memory.
When writing data in the NAND flash™ memory, data must be written after erasing data in a block serving as a minimum erasable unit. Accordingly, when writing data, an erased block (erasure block) is first prepared, and a page to be rewritten and data not to be rewritten in a block need be copied in the erasure block.
Since such erasure block is generated, a memory controller must complexly manage a plurality of physical tables allocated on a RAM based on the address translation table (L2P (Logical to Physical) table) scheme.
Thus, the numbers of determination and detection processes increase, the processing speed decreases, and the complexity of processes increases to manage the above described physical tables. Such determination and detection processes need to be frequently performed in a normal rewrite operation of write/erase access. This largely influences and degrades the performance of the entire memory.